1) Field of the Invention
This invention relates generally to fabrication of Semiconductor devices having Electro Static Discharge (ESD) circuits and more particularly to a Ge implant process to improve the performance of Electro Static Discharge (ESD) transistors.
2) Description of the Prior Art
In current processes, the Electro Static Discharge (ESD) device often uses the snapback characteristics of parasitic bipolar of NMOS transistor to carry away the high current pulse. Because of the p-well, the emitter injection efficiency is low. So the ESD device can not have high performance, especially for deep sub-micron devices with higher p-well concentrations which will degrade the current gain.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,413,969 (Huang): Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process--shows a Ge implant into S/D regions in a silicide process for ESD. Selective salicidation of source/drain regions of a transistor is accomplished by Ge I/I a first subset of the source/drain regions to hinder formation of metal-silicide over the first subset of the source/drain regions. See col. 4, line 63.
U.S. Pat. No. 5,496,751 (Wei) Method of forming an ESD and hot carrier resistant integrated circuit structure--shows a method of forming a ESD device using LATID I/I processes.
U.S. Pat. No. 5,360,749 (Anjum)--Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface--shows a method of tilt angle I/I Ge into S/D regions and in a portion of the channel. The semiconductor structure is adapted to receive non-perpendicular implant of germanium in the juncture between the channel and the source/drain regions as well as in the juncture between field oxide channel stop implant and source/drain regions.
U.S. Pat. No. 5,312,766 (Aronowitz) Method of providing lower contact resistance in MOS transistors--shows Ge implanted immediately on the substrate surface of a FET.